REALIZATION OF LOW TRANSITION BASED PRPG FOR POWER OPTIMIZED APPLICATIONS

This paper proposes low power pseudo random test pattern generator. This produces the necessary test patterns which are used for running the circuit under test for detecting faults. Power consumption of the circuit under test is measured by switching activity of the inside logic which depends on the randomness of applied stimulus. Power consumption is greatly increased due to the reduction of correlation between the successive vectors of applied stimulus. A modified conventional linear feedback shift register is implemented for reducing power of circuit under test by generating the patterns by reducing the utilization of hard ware. The main intension of producing intermediate patterns is to reduce the conventional activity of primary inputs (PI) that which reduces the switching activities inside the CUT and by this power consumption is reduced without using huge hardware